Vlsi Implementation of N X N Parallel Decimal Multiplier Using Csa

This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that uses a novel BCD–4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. Decimal floating-point multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. The novelty of the design is that it is the first parallel decimal floating-point multiplier offering low latency and high throughput. This design is based on a previously published parallel fixed-point decimal multiplier which uses alternate decimal digit encodings to reduce area and delay. The corresponding hardware algorithms are normally composed of three steps: partial product generation (PPG), partial product reduction (PPR), and final carry propagating addition. In order to improve the speed of parallel decimal multiplication, we presenta new PPG method, fine tune the PPR method of one of the full solutions and the final addition scheme of the other; thus assembling a new full solution. Logical Effort analysis and 0.13 μm synthesis show at least 13% speed advantage, but at a cost of at most 36% additional area consumption.